# m-labs/migen

A Python toolbox for building complex digital hardware

Repository: https://github.com/m-labs/migen
Canonical: https://ross.abutalabs.com/products/migen
Homepage: https://m-labs.hk/migen
Language: Python
License: NOASSERTION
License Family: other
Archived: true
Last push: 2026-01-05T04:05:22+00:00

## Health v2 (maintenance only)
Score: 10/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 60, release rhythm 35, longevity 100
- inputs: {"age_days": 5386, "days_push": 240, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, archived, no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1328, forks 219 (observed 2026-08-28T04:04:23.634645+00:00)

## What it is
Migen is a Python-based toolbox for building complex digital hardware, replacing the event-driven paradigm of Verilog/VHDL with combinatorial and synchronous statements while allowing logic to be generated by Python programs. It includes libraries for system-on-chip interconnect, dataflow programming, high-level synthesis, and Python-based simulation.

## Use cases
- generate FPGA logic with Python instead of Verilog
- build a system-on-chip design programmatically
- write hardware test benches in Python
- synthesize Python routines into state machines with datapaths
- create reusable, parameterized hardware designs via metaprogramming
- design ASIC or FPGA circuits with sane integer arithmetic

## When to choose
- you want to leverage Python's expressiveness for hardware design
- you are building synchronous digital circuits and find Verilog/VHDL tedious
- you need procedural generation of logic beyond HDL generate statements
- you are working on MiSoC or ARTIQ-related hardware

## When to avoid
- you need an industry-standard HDL flow with existing Verilog/VHDL toolchain integration
- your design is primarily asynchronous or event-driven
- you need a large community and ecosystem like Chisel or SystemVerilog
- you require commercial vendor support

## Facets
- artifact type: library
- maturity: maintenance
- function: compiler, simulation, developer-tools
- domain: hardware, embedded-systems
- platform: python, cross-platform
- tags: hdl, fpga, asic, hardware-design, fhdl, misoc, metaprogramming, automation

## Member repositories
- m-labs/migen (main) score 10

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:23.634645+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T04:45:58.553829+00:00, confidence not recorded.
  - readme: https://github.com/m-labs/migen (fetched 2026-08-28T04:04:23.634645+00:00, sha 83ab65f3226c)
  - homepage: https://m-labs.hk/migen (fetched 2026-08-29T12:05:03.759542+00:00, sha 6d37422fc88c)
  - site_page: https://m-labs.hk/about-us/company (fetched 2026-08-29T12:05:03.768562+00:00, sha f31a70a1511d)
  - site_page: https://m-labs.hk/about-us/faq (fetched 2026-08-29T12:05:03.770418+00:00, sha ba069a0211b7)
  - site_page: https://m-labs.hk/about-us/jobs (fetched 2026-08-29T12:05:03.772281+00:00, sha 5422d86c3e65)
  - site_page: https://m-labs.hk/about-us/office (fetched 2026-08-29T12:05:03.773855+00:00, sha 8d066ade5d43)
  - registry_pypi: https://pypi.org/pypi/migen/json (fetched 2026-08-29T12:05:03.776997+00:00, sha 55a6cbd911be)
- Data as of 2026-08-30T08:39:29.467469+00:00.