enjoy-digital/litex

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

4061 stars · 748 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

LiteX is a Python-based framework for building FPGA cores and Systems-on-Chip, providing buses, common cores, CPU integration, and build backends for open-source and vendor toolchains. It enables rapid creation of complex, portable FPGA-based systems with mixed-language (Verilog/VHDL) support and simulation via Verilator.

Use cases

• build a custom SoC for an FPGA
• create a RISC-V based system on chip
• integrate DRAM, PCIe, Ethernet cores into an FPGA design
• simulate FPGA designs quickly with Verilator
• port an SoC design across different FPGA vendors
• run Linux on a cheap FPGA board
• explore digital design architectures

When to choose

• you want to build FPGA SoCs quickly with reusable components
• you need portability across FPGA vendors and toolchains
• you want Python-based hardware design with mixed Verilog/VHDL integration
• you need a Linux-capable SoC on an FPGA

When to avoid

• you need a simple single-gate or pure RTL project without SoC structure
• your team works exclusively in raw Verilog/VHDL without Python
• you target ASIC flows rather than FPGA

Facets

framework · maturity active

simulation build-tool developer-tools embedded-systems hardware developer-tools windows python cross-platform fpga system-on-chip soc verilog vhdl migen risc-v hardware-description wishbone axi linux macos

Member repositories

For agents

markdown · JSON · MCP: product_card(name="enjoy-digital/litex")