# enjoy-digital/litex

Build your hardware, easily!

Repository: https://github.com/enjoy-digital/litex
Canonical: https://ross.abutalabs.com/products/litex
Language: Verilog
License: NOASSERTION
License Family: other
Topics: fpga, hardware, system-on-chip
Last push: 2026-08-26T18:13:01+00:00

## Health v2 (maintenance only)
Score: 86/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 62, longevity 100
- inputs: {"age_days": 3952, "days_push": 7, "days_rel": 99, "gap_med": 129.5, "n_releases_24m": 5}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 4061, forks 748 (observed 2026-08-28T04:08:34.004478+00:00)

## What it is
LiteX is a Python-based framework for building FPGA cores and Systems-on-Chip, providing buses, common cores, CPU integration, and build backends for open-source and vendor toolchains. It enables rapid creation of complex, portable FPGA-based systems with mixed-language (Verilog/VHDL) support and simulation via Verilator.

## Use cases
- build a custom SoC for an FPGA
- create a RISC-V based system on chip
- integrate DRAM, PCIe, Ethernet cores into an FPGA design
- simulate FPGA designs quickly with Verilator
- port an SoC design across different FPGA vendors
- run Linux on a cheap FPGA board
- explore digital design architectures

## When to choose
- you want to build FPGA SoCs quickly with reusable components
- you need portability across FPGA vendors and toolchains
- you want Python-based hardware design with mixed Verilog/VHDL integration
- you need a Linux-capable SoC on an FPGA

## When to avoid
- you need a simple single-gate or pure RTL project without SoC structure
- your team works exclusively in raw Verilog/VHDL without Python
- you target ASIC flows rather than FPGA

## Facets
- artifact type: framework
- maturity: active
- function: simulation, build-tool, developer-tools
- domain: embedded-systems, hardware, developer-tools
- platform: windows, python, cross-platform
- tags: fpga, system-on-chip, soc, verilog, vhdl, migen, risc-v, hardware-description, wishbone, axi, linux, macos

## Member repositories
- enjoy-digital/litex (main) score 86

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:08:34.004478+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:23:35.337278+00:00, confidence not recorded.
  - readme: https://github.com/enjoy-digital/litex (fetched 2026-08-28T04:08:34.004478+00:00, sha 787a9f93c60d)
- Data as of 2026-08-30T08:39:29.467469+00:00.