BrunoLevy/learn-fpga resource

Health v2 · maintenance only

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3651 stars · 343 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

A teaching repository for learning FPGA development, Verilog, yosys/nextpnr tooling, and RISC-V processor design, including the minimalistic FemtoRV RISC-V core and SoC. It provides step-by-step tutorials from blinking an LED to building a pipelined RV32IMFC processor on cheap boards like the Lattice IceStick.

Use cases

• learn FPGA development from scratch
• build your own RISC-V processor step by step
• teach a university course on processor design on a budget
• run a minimal RISC-V softcore on a Lattice IceStick
• learn how pipelined CPU design works
• assemble a SoC with LiteX using FemtoRV

When to choose

• you want beginner-friendly, well-documented Verilog for learning CPU and FPGA design
• you need low-cost teaching material for RISC-V and digital design
• you want a tiny readable RISC-V core to study or modify

When to avoid

• you need a production-grade, high-performance RISC-V core
• you want a commercial-grade SoC with full verification and support
• you need advanced FPGA features like PCIe, DDR, or multi-core

Facets

learning-resource · maturity active

developer-tools simulation embedded education hardware embedded-systems programming-languages cross-platform cli fpga risc-v yosys nextpnr verilog soc femtorv processor-design tutorials

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