# BrunoLevy/learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

Repository: https://github.com/BrunoLevy/learn-fpga
Canonical: https://ross.abutalabs.com/products/learn-fpga
Language: C++
License: BSD-3-Clause
License Family: permissive
Last push: 2025-11-18T13:48:23+00:00

## Health v2 (maintenance only)
Score: 56/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 52, release rhythm 35, longevity 100
- inputs: {"age_days": 2289, "days_push": 288, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3651, forks 343 (observed 2026-08-28T04:08:13.053888+00:00)

## What it is
A teaching repository for learning FPGA development, Verilog, yosys/nextpnr tooling, and RISC-V processor design, including the minimalistic FemtoRV RISC-V core and SoC. It provides step-by-step tutorials from blinking an LED to building a pipelined RV32IMFC processor on cheap boards like the Lattice IceStick.

## Use cases
- learn FPGA development from scratch
- build your own RISC-V processor step by step
- teach a university course on processor design on a budget
- run a minimal RISC-V softcore on a Lattice IceStick
- learn how pipelined CPU design works
- assemble a SoC with LiteX using FemtoRV

## When to choose
- you want beginner-friendly, well-documented Verilog for learning CPU and FPGA design
- you need low-cost teaching material for RISC-V and digital design
- you want a tiny readable RISC-V core to study or modify

## When to avoid
- you need a production-grade, high-performance RISC-V core
- you want a commercial-grade SoC with full verification and support
- you need advanced FPGA features like PCIe, DDR, or multi-core

## Facets
- artifact type: learning-resource
- maturity: active
- function: developer-tools, simulation, embedded
- domain: education, hardware, embedded-systems, programming-languages
- platform: cross-platform, cli
- tags: fpga, risc-v, yosys, nextpnr, verilog, soc, femtorv, processor-design, tutorials

## Member repositories
- BrunoLevy/learn-fpga (main) score 56

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:08:13.053888+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:31:41.034200+00:00, confidence not recorded.
  - readme: https://github.com/BrunoLevy/learn-fpga (fetched 2026-08-28T04:08:13.053888+00:00, sha d9b666dfd570)
- Data as of 2026-08-30T08:39:29.467469+00:00.