steveicarus/iverilog

Health v2 · maintenance only

Adoption not part of the score

3609 stars · 623 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

Icarus Verilog is an open-source Verilog HDL compilation system that compiles IEEE 1364 Verilog and a growing subset of SystemVerilog (IEEE 1800) into code for back-end simulation and synthesis tools. It includes the vvp simulation engine, a preprocessor, and code generators targeting simulation, FPGA, PAL, and other formats.

Use cases

• compile and simulate Verilog testbenches from the command line
• simulate SystemVerilog designs for FPGA development
• generate netlists like BLIF or FPGA targets from Verilog source
• run regression tests on RTL designs
• extend simulation with VPI/PLI modules

When to choose

• you need a free, lightweight Verilog simulator for learning or CI
• you want command-line Verilog compilation and simulation on Linux/macOS/Windows
• you need a compiler front-end for Verilog tooling or custom code generators

When to avoid

• you need full SystemVerilog support or high-performance commercial-grade simulation
• you require advanced verification features like UVM or constrained randomization
• you need vendor-specific synthesis or timing analysis

Facets

cli-tool · maturity active

compiler interpreter simulation developer-tools hardware developer-tools simulation windows cross-platform cli verilog systemverilog hdl hardware-description-language vvp vpi fpga eda linux macos

Member repositories

For agents

markdown · JSON · MCP: product_card(name="steveicarus/iverilog")