# steveicarus/iverilog

Icarus Verilog

Repository: https://github.com/steveicarus/iverilog
Canonical: https://ross.abutalabs.com/products/iverilog
Homepage: https://steveicarus.github.io/iverilog/
Language: C++
License: GPL-2.0
License Family: copyleft
Last push: 2026-08-23T21:30:59+00:00

## Health v2 (maintenance only)
Score: 79/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 40, longevity 100
- inputs: {"age_days": 6687, "days_push": 10, "days_rel": 185, "gap_med": null, "n_releases_24m": 1}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3609, forks 623 (observed 2026-08-28T04:08:11.581596+00:00)

## What it is
Icarus Verilog is an open-source Verilog HDL compilation system that compiles IEEE 1364 Verilog and a growing subset of SystemVerilog (IEEE 1800) into code for back-end simulation and synthesis tools. It includes the vvp simulation engine, a preprocessor, and code generators targeting simulation, FPGA, PAL, and other formats.

## Use cases
- compile and simulate Verilog testbenches from the command line
- simulate SystemVerilog designs for FPGA development
- generate netlists like BLIF or FPGA targets from Verilog source
- run regression tests on RTL designs
- extend simulation with VPI/PLI modules

## When to choose
- you need a free, lightweight Verilog simulator for learning or CI
- you want command-line Verilog compilation and simulation on Linux/macOS/Windows
- you need a compiler front-end for Verilog tooling or custom code generators

## When to avoid
- you need full SystemVerilog support or high-performance commercial-grade simulation
- you require advanced verification features like UVM or constrained randomization
- you need vendor-specific synthesis or timing analysis

## Facets
- artifact type: cli-tool
- maturity: active
- function: compiler, interpreter, simulation, developer-tools
- domain: hardware, developer-tools, simulation
- platform: windows, cross-platform, cli
- tags: verilog, systemverilog, hdl, hardware-description-language, vvp, vpi, fpga, eda, linux, macos

## Member repositories
- steveicarus/iverilog (main) score 79

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:08:11.581596+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:33:40.483044+00:00, confidence not recorded.
  - readme: https://github.com/steveicarus/iverilog (fetched 2026-08-28T04:08:11.581596+00:00, sha 1ed9d8bef3e2)
  - homepage: https://steveicarus.github.io/iverilog/ (fetched 2026-08-29T09:26:50.530820+00:00, sha 83b1f929d6a4)
- Data as of 2026-08-30T08:39:29.467469+00:00.