analogdevicesinc/hdl

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

2000 stars · 1679 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Analog Devices' HDL (Verilog/VHDL) libraries and FPGA reference design projects for their evaluation boards, built with AMD Xilinx Vivado or Intel Quartus tool chains. It includes reusable IP cores such as JESD204B/C interface framework, AXI ADC/DAC blocks, and SPI Engine, plus Tcl build scripts.

Use cases

• build FPGA bitstreams for Analog Devices evaluation boards
• integrate JESD204B/C ADC/DAC interfaces into an FPGA design
• reuse AXI-based IP cores in custom Xilinx or Intel FPGA projects
• prototype high-speed data converter systems with FPGAs
• port or customize ADI reference designs for custom hardware

When to choose

• you are using an Analog Devices FPGA carrier or evaluation board
• you need proven HDL IP for JESD204B/C or AXI data converter interfaces
• you want a maintained reference design targeting Vivado or Quartus

When to avoid

• you need a general-purpose FPGA framework unrelated to Analog Devices hardware
• you require commercial datasheet-level support rather than community EngineerZone support
• your project targets ASICs or non-Xilinx/Intel FPGA tool chains

Facets

library · maturity active

embedded sdk developer-tools hardware embedded-systems developer-tools embedded verilog vhdl fpga jesd204b xilinx-vivado intel-quartus reference-designs analog-devices ip-cores axi

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