# analogdevicesinc/hdl

HDL libraries and projects

Repository: https://github.com/analogdevicesinc/hdl
Canonical: https://ross.abutalabs.com/products/hdl
Homepage: http://analogdevicesinc.github.io/hdl/
Language: Verilog
License: NOASSERTION
License Family: other
Topics: analog-devices, hdl, jesd204b, verilog, fpga, hacktoberfest
Last push: 2026-08-26T14:43:41+00:00

## Health v2 (maintenance only)
Score: 70/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 16, longevity 100
- inputs: {"age_days": 4577, "days_push": 7, "days_rel": 525, "gap_med": 124, "n_releases_24m": 2}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2000, forks 1679 (observed 2026-08-28T04:06:03.854036+00:00)

## What it is
Analog Devices' HDL (Verilog/VHDL) libraries and FPGA reference design projects for their evaluation boards, built with AMD Xilinx Vivado or Intel Quartus tool chains. It includes reusable IP cores such as JESD204B/C interface framework, AXI ADC/DAC blocks, and SPI Engine, plus Tcl build scripts.

## Use cases
- build FPGA bitstreams for Analog Devices evaluation boards
- integrate JESD204B/C ADC/DAC interfaces into an FPGA design
- reuse AXI-based IP cores in custom Xilinx or Intel FPGA projects
- prototype high-speed data converter systems with FPGAs
- port or customize ADI reference designs for custom hardware

## When to choose
- you are using an Analog Devices FPGA carrier or evaluation board
- you need proven HDL IP for JESD204B/C or AXI data converter interfaces
- you want a maintained reference design targeting Vivado or Quartus

## When to avoid
- you need a general-purpose FPGA framework unrelated to Analog Devices hardware
- you require commercial datasheet-level support rather than community EngineerZone support
- your project targets ASICs or non-Xilinx/Intel FPGA tool chains

## Facets
- artifact type: library
- maturity: active
- function: embedded, sdk, developer-tools
- domain: hardware, embedded-systems, developer-tools
- platform: embedded
- tags: verilog, vhdl, fpga, jesd204b, xilinx-vivado, intel-quartus, reference-designs, analog-devices, ip-cores, axi

## Member repositories
- analogdevicesinc/hdl (main) score 70

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:03.854036+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:02:07.059154+00:00, confidence not recorded.
  - readme: https://github.com/analogdevicesinc/hdl (fetched 2026-08-28T04:06:03.854036+00:00, sha a790a453f4e4)
  - homepage: http://analogdevicesinc.github.io/hdl/ (fetched 2026-08-29T10:41:46.486805+00:00, sha 85a28a8d8c92)
- Data as of 2026-08-30T08:39:29.467469+00:00.