olofk/fusesoc

Health v2 · maintenance only

Adoption not part of the score

1453 stars · 280 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

FuseSoC is a package manager and build abstraction tool for HDL (Verilog/VHDL) code, aimed at increasing reuse of IP cores and simplifying building and simulating SoC designs. It is a Python-based CLI that manages core libraries, drives multiple FPGA/simulator backends, and supports regression testing and CI.

Use cases

• manage reusable FPGA IP core libraries
• build FPGA bitstreams from Verilog or VHDL designs
• run regression simulations across multiple HDL simulators
• port an RTL design to new FPGA targets
• set up continuous integration for hardware projects
• generate FPGA SBOMs for compliance

When to choose

• you develop FPGA or ASIC designs in Verilog/VHDL and want IP reuse
• you need a vendor-neutral build abstraction across FPGA tools and simulators
• you want to run automated HDL regression tests in CI
• you maintain multiple hardware targets or boards from one codebase

When to avoid

• you only use a single vendor's IDE flow and don't need portability
• your project is software-only with no HDL code
• you need graphical EDA tooling rather than a command-line workflow

Facets

cli-tool · maturity active

package-manager build-tool testing cli developer-tools developer-tools hardware embedded-systems windows python cli fpga asic hdl verilog vhdl ip-cores eda simulation soc automation linux macos

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