# olofk/fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

Repository: https://github.com/olofk/fusesoc
Canonical: https://ross.abutalabs.com/products/fusesoc
Language: Python
License: BSD-2-Clause
License Family: permissive
Topics: python, eda, reuse, package-manager, fpga, verilog, vhdl
Last push: 2026-08-24T12:37:32+00:00

## Health v2 (maintenance only)
Score: 85/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 59, longevity 100
- inputs: {"age_days": 4579, "days_push": 9, "days_rel": 114, "gap_med": 105.5, "n_releases_24m": 7}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1453, forks 280 (observed 2026-08-28T04:04:46.554579+00:00)

## What it is
FuseSoC is a package manager and build abstraction tool for HDL (Verilog/VHDL) code, aimed at increasing reuse of IP cores and simplifying building and simulating SoC designs. It is a Python-based CLI that manages core libraries, drives multiple FPGA/simulator backends, and supports regression testing and CI.

## Use cases
- manage reusable FPGA IP core libraries
- build FPGA bitstreams from Verilog or VHDL designs
- run regression simulations across multiple HDL simulators
- port an RTL design to new FPGA targets
- set up continuous integration for hardware projects
- generate FPGA SBOMs for compliance

## When to choose
- you develop FPGA or ASIC designs in Verilog/VHDL and want IP reuse
- you need a vendor-neutral build abstraction across FPGA tools and simulators
- you want to run automated HDL regression tests in CI
- you maintain multiple hardware targets or boards from one codebase

## When to avoid
- you only use a single vendor's IDE flow and don't need portability
- your project is software-only with no HDL code
- you need graphical EDA tooling rather than a command-line workflow

## Facets
- artifact type: cli-tool
- maturity: active
- function: package-manager, build-tool, testing, cli, developer-tools
- domain: developer-tools, hardware, embedded-systems
- platform: windows, python, cli
- tags: fpga, asic, hdl, verilog, vhdl, ip-cores, eda, simulation, soc, automation, linux, macos

## Member repositories
- olofk/fusesoc (main) score 85

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:46.554579+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T04:35:45.591220+00:00, confidence not recorded.
  - readme: https://github.com/olofk/fusesoc (fetched 2026-08-28T04:04:46.554579+00:00, sha edb04e9afbbd)
  - registry_pypi: https://pypi.org/pypi/fusesoc/json (fetched 2026-08-29T11:45:03.335318+00:00, sha 290745e06f22)
- Data as of 2026-08-30T08:39:29.467469+00:00.