firesim/firesim

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

1050 stars · 275 forks observed · 2026-10-14

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

FireSim is an open-source FPGA-accelerated full-system hardware simulation platform for validating, profiling, and debugging RTL hardware implementations at tens to hundreds of MHz. It scales from single SoC simulations on on-prem FPGAs (e.g., Xilinx Alveo) to datacenter-scale simulations using hundreds of cloud FPGAs (e.g., AWS EC2 F1).

Use cases

• simulate RISC-V SoC designs on FPGAs
• validate and debug RTL hardware implementations
• run datacenter-scale hardware simulations on AWS EC2 F1
• co-simulate ASIC RTL with cycle-accurate I/O models
• profile and benchmark computer architecture designs
• simulate Rocket Chip and BOOM processors
• research networking, security, and systems on simulated hardware

When to choose

• you need fast, cycle-accurate full-system hardware simulation
• you want to scale simulations from one FPGA to hundreds of cloud FPGAs
• you are doing computer architecture research with RISC-V designs
• you need to validate RTL before tape-out
• you want an open-source, well-documented simulation platform with an active community

When to avoid

• you only need functional software emulation without cycle accuracy
• you do not have access to supported FPGA hardware (AWS F1, Alveo U250/U280, VCU118, Nitefury II)
• you need simulation of non-RISC-V ISAs or unsupported SoC designs
• you want a lightweight instruction-set simulator rather than FPGA-based simulation

Facets

framework · maturity active

simulation developer-tools cloud computer-vision hardware cloud-computing developer-tools cloud python jvm fpga risc-v hardware-simulation rtl-simulation cycle-accurate aws-ec2-f1 xilinx-alveo rocket-chip datacenter-scale computer-architecture research linux

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markdown · JSON · MCP: product_card(name="firesim/firesim")