# firesim/firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Repository: https://github.com/firesim/firesim
Canonical: https://ross.abutalabs.com/products/firesim
Homepage: https://fires.im
Language: Scala
License: NOASSERTION
License Family: other
Topics: fpga, risc-v, simulation, datacenter, hardware, firesim, rocket-chip, boom, on-prem, cloud
Last push: 2026-08-31T17:20:45+00:00

## Health v2 (maintenance only)
Score: 85/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 100, release rhythm 57, longevity 100
- inputs: {"age_days": 3034, "days_push": 2, "days_rel": 73, "gap_med": null, "n_releases_24m": 1}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1038, forks 273 (observed 2026-09-01T02:14:01.430645+00:00)

## What it is
FireSim is an open-source FPGA-accelerated full-system hardware simulation platform for validating, profiling, and debugging RTL hardware implementations at tens to hundreds of MHz. It scales from single SoC simulations on on-prem FPGAs (e.g., Xilinx Alveo) to datacenter-scale simulations using hundreds of cloud FPGAs (e.g., AWS EC2 F1).

## Use cases
- simulate RISC-V SoC designs on FPGAs
- validate and debug RTL hardware implementations
- run datacenter-scale hardware simulations on AWS EC2 F1
- co-simulate ASIC RTL with cycle-accurate I/O models
- profile and benchmark computer architecture designs
- simulate Rocket Chip and BOOM processors
- research networking, security, and systems on simulated hardware

## When to choose
- you need fast, cycle-accurate full-system hardware simulation
- you want to scale simulations from one FPGA to hundreds of cloud FPGAs
- you are doing computer architecture research with RISC-V designs
- you need to validate RTL before tape-out
- you want an open-source, well-documented simulation platform with an active community

## When to avoid
- you only need functional software emulation without cycle accuracy
- you do not have access to supported FPGA hardware (AWS F1, Alveo U250/U280, VCU118, Nitefury II)
- you need simulation of non-RISC-V ISAs or unsupported SoC designs
- you want a lightweight instruction-set simulator rather than FPGA-based simulation

## Facets
- artifact type: framework
- maturity: active
- function: simulation, developer-tools, cloud
- domain: computer-vision, hardware, cloud-computing, developer-tools
- platform: cloud, python, jvm
- tags: fpga, risc-v, hardware-simulation, rtl-simulation, cycle-accurate, aws-ec2-f1, xilinx-alveo, rocket-chip, datacenter-scale, computer-architecture, research, linux

## Member repositories
- firesim/firesim (main) score 85

## Provenance
- Observed fields: from GitHub, fetched 2026-09-01T02:14:01.430645+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T07:04:39.901957+00:00, confidence not recorded.
  - readme: https://github.com/firesim/firesim (fetched 2026-09-01T02:14:01.430645+00:00, sha 76edec9f510e)
  - homepage: https://fires.im (fetched 2026-08-29T13:09:08.079111+00:00, sha 51797d66e07d)
  - site_page: https://fires.im/about (fetched 2026-08-29T13:09:08.082276+00:00, sha 5fd058cc14b5)
- Data as of 2026-08-30T08:39:29.467469+00:00.