darklife/darkriscv

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

2601 stars · 328 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

DarkRISCV is an open-source RISC-V CPU softcore implemented from scratch in Verilog, supporting RV32E/RV32I and running on a wide range of Xilinx, Altera, and Lattice FPGAs. It is a compact, high-frequency core (850-1500 LUTs, up to 250MHz on Ultrascale) designed for experimentation, education, and FPGA integration.

Use cases

• implement a RISC-V CPU core on an FPGA
• learn how a pipelined RISC-V processor works in Verilog
• simulate a RISC-V core with Icarus Verilog and inspect waveforms
• integrate a small softcore into an FPGA SoC design
• experiment with RV32E embedded RISC-V implementations
• compare RISC-V core performance across FPGA families

When to choose

• you need a small, hackable RISC-V softcore for FPGA projects
• you want readable Verilog source to learn CPU design
• you need a core that fits in tiny FPGAs like Spartan-3E
• you want to run RISC-V firmware in simulation quickly with make

When to avoid

• you need a production-grade core with full privilege spec, MMU, and interlocks
• you need RV64 or full RV32IMAFC support
• you require certified or formally verified processor IP
• you want a high-IPC out-of-order core for performance-critical workloads

Facets

library · maturity active

simulation embedded hardware embedded-systems cross-platform risc-v verilog fpga cpu-core rtl softcore

Member repositories

For agents

markdown · JSON · MCP: product_card(name="darklife/darkriscv")