# darklife/darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Repository: https://github.com/darklife/darkriscv
Canonical: https://ross.abutalabs.com/products/darkriscv
Language: Verilog
License: BSD-3-Clause
License Family: permissive
Topics: riscv, verilog, risc-v, fpga, core
Last push: 2026-05-12T04:31:28+00:00

## Health v2 (maintenance only)
Score: 69/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 82, release rhythm 35, longevity 100
- inputs: {"age_days": 2936, "days_push": 113, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2601, forks 328 (observed 2026-08-28T04:07:03.319175+00:00)

## What it is
DarkRISCV is an open-source RISC-V CPU softcore implemented from scratch in Verilog, supporting RV32E/RV32I and running on a wide range of Xilinx, Altera, and Lattice FPGAs. It is a compact, high-frequency core (850-1500 LUTs, up to 250MHz on Ultrascale) designed for experimentation, education, and FPGA integration.

## Use cases
- implement a RISC-V CPU core on an FPGA
- learn how a pipelined RISC-V processor works in Verilog
- simulate a RISC-V core with Icarus Verilog and inspect waveforms
- integrate a small softcore into an FPGA SoC design
- experiment with RV32E embedded RISC-V implementations
- compare RISC-V core performance across FPGA families

## When to choose
- you need a small, hackable RISC-V softcore for FPGA projects
- you want readable Verilog source to learn CPU design
- you need a core that fits in tiny FPGAs like Spartan-3E
- you want to run RISC-V firmware in simulation quickly with make

## When to avoid
- you need a production-grade core with full privilege spec, MMU, and interlocks
- you need RV64 or full RV32IMAFC support
- you require certified or formally verified processor IP
- you want a high-IPC out-of-order core for performance-critical workloads

## Facets
- artifact type: library
- maturity: active
- function: simulation, embedded
- domain: hardware, embedded-systems
- platform: cross-platform
- tags: risc-v, verilog, fpga, cpu-core, rtl, softcore

## Member repositories
- darklife/darkriscv (main) score 69

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:07:03.319175+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:21:10.467049+00:00, confidence not recorded.
  - readme: https://github.com/darklife/darkriscv (fetched 2026-08-28T04:07:03.319175+00:00, sha bc18dbaa99af)
- Data as of 2026-08-30T08:39:29.467469+00:00.