SlugLab/CXLMemSim

Health v2 · maintenance only

Adoption not part of the score

1092 stars · 63 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

CXLMemSim is a simulation and emulation framework for CXL 3.0 memory systems, combining a latency/bandwidth/topology/coherency simulator with a QEMU-integrated CXL device emulation stack for Type 3 memory and experimental Type 2 GPU devices. It enables full-system CXL experiments without real CXL hardware.

Use cases

• simulate CXL memory latency and bandwidth without hardware
• emulate CXL Type 3 memory devices in QEMU
• study memory pooling and tiering policies over CXL
• test CXL coherency and directory behavior
• evaluate memory placement and migration policies
• experiment with CXL Type 2 GPU/accelerator devices
• run full-system CXL research experiments with gem5 or QEMU

When to choose

• you need application-visible CXL memory performance estimates without physical CXL hardware
• you want full-system experiments with a realistic CXL device interface
• you are researching CXL memory pooling, tiering, or coherency
• you need a CUDA-compatible shim to prototype CXL-attached accelerators

When to avoid

• you need cycle-accurate silicon-level CXL protocol verification
• you want production deployment of CXL memory rather than research simulation
• you need a quick benchmark of real hardware rather than a modeling tool

Facets

framework · maturity active

simulation developer-tools benchmarking monitoring hardware simulation developer-tools microservices cpp c self-hosted cxl memory-systems qemu gem5 memory-pooling full-system-emulation computer-architecture research linux docker

Member repositories

For agents

markdown · JSON · MCP: product_card(name="SlugLab/CXLMemSim")