# SlugLab/CXLMemSim

CXLMemSim: Practical Performance Simulation and Characterization of CXL 3.0 Memory Systems

Repository: https://github.com/SlugLab/CXLMemSim
Canonical: https://ross.abutalabs.com/products/cxlmemsim
Homepage: https://dl.acm.org/doi/10.1145/3806645.3820069
Language: C
License: BSD-3-Clause
License Family: permissive
Last push: 2026-08-22T21:03:27+00:00

## Health v2 (maintenance only)
Score: 70/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 17, longevity 100
- inputs: {"age_days": 1435, "days_push": 11, "days_rel": 340, "gap_med": null, "n_releases_24m": 1}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1092, forks 63 (observed 2026-08-28T04:03:33.291397+00:00)

## What it is
CXLMemSim is a simulation and emulation framework for CXL 3.0 memory systems, combining a latency/bandwidth/topology/coherency simulator with a QEMU-integrated CXL device emulation stack for Type 3 memory and experimental Type 2 GPU devices. It enables full-system CXL experiments without real CXL hardware.

## Use cases
- simulate CXL memory latency and bandwidth without hardware
- emulate CXL Type 3 memory devices in QEMU
- study memory pooling and tiering policies over CXL
- test CXL coherency and directory behavior
- evaluate memory placement and migration policies
- experiment with CXL Type 2 GPU/accelerator devices
- run full-system CXL research experiments with gem5 or QEMU

## When to choose
- you need application-visible CXL memory performance estimates without physical CXL hardware
- you want full-system experiments with a realistic CXL device interface
- you are researching CXL memory pooling, tiering, or coherency
- you need a CUDA-compatible shim to prototype CXL-attached accelerators

## When to avoid
- you need cycle-accurate silicon-level CXL protocol verification
- you want production deployment of CXL memory rather than research simulation
- you need a quick benchmark of real hardware rather than a modeling tool

## Facets
- artifact type: framework
- maturity: active
- function: simulation, developer-tools, benchmarking, monitoring
- domain: hardware, simulation, developer-tools, microservices
- platform: cpp, c, self-hosted
- tags: cxl, memory-systems, qemu, gem5, memory-pooling, full-system-emulation, computer-architecture, research, linux, docker

## Member repositories
- SlugLab/CXLMemSim (main) score 70

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:33.291397+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:49:00.554412+00:00, confidence not recorded.
  - readme: https://github.com/SlugLab/CXLMemSim (fetched 2026-08-28T04:03:33.291397+00:00, sha fdb2f7bae47a)
- Data as of 2026-08-30T08:39:29.467469+00:00.