openhwgroup/cva6

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

3081 stars · 1003 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

CVA6 is an open-source, 6-stage, single-issue, in-order RISC-V CPU core written in SystemVerilog, supporting the 64-bit RV64GC ISA with three privilege levels capable of booting Linux. It is highly configurable for both ASIC and FPGA implementations and serves as the basis for application-class cores in the OpenHW Group CORE-V family.

Use cases

• design a custom RISC-V processor for an FPGA
• integrate an application-class CPU core into an ASIC design
• boot Linux on an open-source RISC-V core
• research CPU microarchitecture like branch prediction and MMU design
• simulate a RISC-V core with Verilator for verification
• build an embedded system around a configurable 64-bit RISC-V core

When to choose

• you need a production-quality, Linux-capable open-source RISC-V core
• you want a heavily parameterizable CPU for ASIC or FPGA targets
• you are doing computer architecture research on a real, well-documented core
• you need RV64GC compliance with M/S/U privilege levels

When to avoid

• you need a small, simple microcontroller-class core rather than an application-class pipeline
• you want an out-of-order or superscalar processor
• you need a soft CPU for a non-RISC-V ISA
• you lack SystemVerilog/FPGA/ASIC design experience and just want a ready-made chip

Facets

library · maturity active

embedded simulation developer-tools hardware embedded-systems operating-systems risc-v cpu-core systemverilog open-source-hardware fpga asic rv64gc ariane processor-design linux

Member repositories

For agents

markdown · JSON · MCP: product_card(name="openhwgroup/cva6")