# openhwgroup/cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Repository: https://github.com/openhwgroup/cva6
Canonical: https://ross.abutalabs.com/products/cva6
Homepage: https://docs.openhwgroup.org/projects/cva6-user-manual/
Language: Assembly
License: NOASSERTION
License Family: other
Topics: systemverilog-hdl, cpu, asic, fpga, rv64gc, ariane, risc-v
Last push: 2026-08-26T14:33:12+00:00

## Health v2 (maintenance only)
Score: 74/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 28, longevity 100
- inputs: {"age_days": 3144, "days_push": 7, "days_rel": 497, "gap_med": 48.0, "n_releases_24m": 3}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3081, forks 1003 (observed 2026-08-28T04:07:41.865943+00:00)

## What it is
CVA6 is an open-source, 6-stage, single-issue, in-order RISC-V CPU core written in SystemVerilog, supporting the 64-bit RV64GC ISA with three privilege levels capable of booting Linux. It is highly configurable for both ASIC and FPGA implementations and serves as the basis for application-class cores in the OpenHW Group CORE-V family.

## Use cases
- design a custom RISC-V processor for an FPGA
- integrate an application-class CPU core into an ASIC design
- boot Linux on an open-source RISC-V core
- research CPU microarchitecture like branch prediction and MMU design
- simulate a RISC-V core with Verilator for verification
- build an embedded system around a configurable 64-bit RISC-V core

## When to choose
- you need a production-quality, Linux-capable open-source RISC-V core
- you want a heavily parameterizable CPU for ASIC or FPGA targets
- you are doing computer architecture research on a real, well-documented core
- you need RV64GC compliance with M/S/U privilege levels

## When to avoid
- you need a small, simple microcontroller-class core rather than an application-class pipeline
- you want an out-of-order or superscalar processor
- you need a soft CPU for a non-RISC-V ISA
- you lack SystemVerilog/FPGA/ASIC design experience and just want a ready-made chip

## Facets
- artifact type: library
- maturity: active
- function: embedded, simulation, developer-tools
- domain: hardware, embedded-systems, operating-systems
- platform: -
- tags: risc-v, cpu-core, systemverilog, open-source-hardware, fpga, asic, rv64gc, ariane, processor-design, linux

## Member repositories
- openhwgroup/cva6 (main) score 74

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:07:41.865943+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:46:31.590121+00:00, confidence not recorded.
  - readme: https://github.com/openhwgroup/cva6 (fetched 2026-08-28T04:07:41.865943+00:00, sha 522cd43798b1)
  - homepage: https://docs.openhwgroup.org/projects/cva6-user-manual/ (fetched 2026-08-29T09:43:02.301667+00:00, sha 53efd2f9a00e)
  - site_page: https://docs.openhwgroup.org/projects/cva6-user-manual/04_cv32a65x/index.html (fetched 2026-08-29T09:43:02.310599+00:00, sha d68cb9b16235)
  - site_page: https://docs.openhwgroup.org/projects/cva6-user-manual/07_cv32a60x/index.html (fetched 2026-08-29T09:43:02.312377+00:00, sha 339ecd925099)
  - site_page: https://docs.openhwgroup.org/projects/cva6-user-manual/06_cv64a6_mmu/index.html (fetched 2026-08-29T09:43:02.314681+00:00, sha 377d392dffe0)
- Data as of 2026-08-30T08:39:29.467469+00:00.