openhwgroup/cv32e40p

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

1278 stars · 547 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

CV32E40P is an open-source 32-bit RISC-V processor core (RV32IMFC with PULP extensions) implemented in SystemVerilog, maintained by the OpenHW Group as part of the CORE-V family. It is a 4-stage in-order CPU IP block derived from the PULP-Platform RI5CY core, intended for integration into ASIC and FPGA designs.

Use cases

• integrate an open-source RISC-V CPU core into an ASIC design
• synthesize a 32-bit RISC-V processor for an FPGA
• study RISC-V core RTL implementation in SystemVerilog
• use PULP SIMD and hardware loop extensions for embedded DSP workloads
• build a custom SoC with a verified RV32IMFC core
• experiment with RISC-V core design and verification flows

When to choose

• you need a production-quality, verified open-source RISC-V core with RTL freeze guarantees
• you want PULP custom extensions like hardware loops and SIMD for energy-efficient embedded computing
• you need OBI-compliant bus interfaces for easy SoC integration
• you want a well-documented core with formal and simulation verification results

When to avoid

• you need a 64-bit or out-of-order high-performance processor
• you want a soft CPU for running Linux with MMU support
• you need a complete verification environment - it lives in the separate core-v-verif repository
• you need application-level software rather than hardware RTL

Facets

library · maturity active

embedded simulation compiler embedded-systems hardware developer-tools embedded risc-v cpu-core systemverilog rtl openhw-group pulp rv32imfc processor-ip hardware-design fpga asic

Member repositories

For agents

markdown · JSON · MCP: product_card(name="openhwgroup/cv32e40p")