# openhwgroup/cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Repository: https://github.com/openhwgroup/cv32e40p
Canonical: https://ross.abutalabs.com/products/cv32e40p
Homepage: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest
Language: SystemVerilog
License: NOASSERTION
License Family: other
Topics: riscv, riscv32imfc
Last push: 2026-08-26T13:01:14+00:00

## Health v2 (maintenance only)
Score: 67/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 8, longevity 100
- inputs: {"age_days": 3849, "days_push": 7, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1278, forks 547 (observed 2026-08-28T04:04:13.407043+00:00)

## What it is
CV32E40P is an open-source 32-bit RISC-V processor core (RV32IMFC with PULP extensions) implemented in SystemVerilog, maintained by the OpenHW Group as part of the CORE-V family. It is a 4-stage in-order CPU IP block derived from the PULP-Platform RI5CY core, intended for integration into ASIC and FPGA designs.

## Use cases
- integrate an open-source RISC-V CPU core into an ASIC design
- synthesize a 32-bit RISC-V processor for an FPGA
- study RISC-V core RTL implementation in SystemVerilog
- use PULP SIMD and hardware loop extensions for embedded DSP workloads
- build a custom SoC with a verified RV32IMFC core
- experiment with RISC-V core design and verification flows

## When to choose
- you need a production-quality, verified open-source RISC-V core with RTL freeze guarantees
- you want PULP custom extensions like hardware loops and SIMD for energy-efficient embedded computing
- you need OBI-compliant bus interfaces for easy SoC integration
- you want a well-documented core with formal and simulation verification results

## When to avoid
- you need a 64-bit or out-of-order high-performance processor
- you want a soft CPU for running Linux with MMU support
- you need a complete verification environment - it lives in the separate core-v-verif repository
- you need application-level software rather than hardware RTL

## Facets
- artifact type: library
- maturity: active
- function: embedded, simulation, compiler
- domain: embedded-systems, hardware, developer-tools
- platform: embedded
- tags: risc-v, cpu-core, systemverilog, rtl, openhw-group, pulp, rv32imfc, processor-ip, hardware-design, fpga, asic

## Member repositories
- openhwgroup/cv32e40p (main) score 67

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:13.407043+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T05:02:46.611572+00:00, confidence not recorded.
  - readme: https://github.com/openhwgroup/cv32e40p (fetched 2026-08-28T04:04:13.407043+00:00, sha afcbe872c3af)
  - homepage: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest (fetched 2026-08-29T12:13:31.577882+00:00, sha d0209443ef96)
  - site_page: https://docs.openhwfoundation.org/projects/cv32e40p-user-manual/en/latest/preface.html (fetched 2026-08-29T12:13:31.587032+00:00, sha 57c7ce9c0934)
  - site_page: https://docs.openhwfoundation.org/projects/cv32e40p-user-manual/en/latest/intro.html (fetched 2026-08-29T12:13:31.589148+00:00, sha 7cf216ccf233)
  - site_page: https://docs.openhwfoundation.org/projects/cv32e40p-user-manual/en/latest/core_versions.html (fetched 2026-08-29T12:13:31.591362+00:00, sha 34e11730b077)
- Data as of 2026-08-30T08:39:29.467469+00:00.