cocotb/cocotb

Health v2 · maintenance only

Adoption not part of the score

2483 stars · 674 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

cocotb is a coroutine-based Python framework for writing testbenches that verify VHDL, Verilog, and SystemVerilog RTL designs via cosimulation. It is simulator-agnostic, working with major simulators like Verilator, ModelSim, VCS, Xcelium, GHDL, and Icarus Verilog.

Use cases

• write RTL testbenches in Python instead of SystemVerilog
• verify VHDL and Verilog chip designs with a Python testbench
• run hardware simulation tests in CI pipelines
• replace UVM with a Python-based verification workflow
• test mixed-language or mixed-signal designs with one framework
• drive a Verilator or Icarus Verilog simulation from Python coroutines

When to choose

• you want to verify RTL designs using Python and its ecosystem instead of HDL testbench languages
• you need simulator-agnostic verification across multiple commercial and open-source simulators
• your team is more productive in Python than in SystemVerilog/UVM
• you want easy CI integration for hardware regression testing

When to avoid

• you need formal verification or static property checking rather than simulation
• your team and existing infrastructure are fully committed to UVM/SystemVerilog methodologies
• you require cycle-accurate synthesis-level performance from the testbench itself
• your simulator is not among the supported cosimulation targets

Facets

framework · maturity stable

testing simulation developer-tools hardware embedded-systems developer-tools testing windows python cross-platform rtl-verification testbench vhdl verilog systemverilog cosimulation hardware-verification chip-design uvm-alternative linux macos

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