# cocotb/cocotb

cocotb: Python-based chip (RTL) verification

Repository: https://github.com/cocotb/cocotb
Canonical: https://ross.abutalabs.com/products/cocotb
Homepage: https://www.cocotb.org
Language: Python
License: BSD-3-Clause
License Family: permissive
Topics: python, vhdl, verilog, uvm, verification, test
Last push: 2026-08-24T23:07:42+00:00

## Health v2 (maintenance only)
Score: 73/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 25, longevity 100
- inputs: {"age_days": 4830, "days_push": 9, "days_rel": 291, "gap_med": 191.5, "n_releases_24m": 3}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2483, forks 674 (observed 2026-08-28T04:06:55.447575+00:00)

## What it is
cocotb is a coroutine-based Python framework for writing testbenches that verify VHDL, Verilog, and SystemVerilog RTL designs via cosimulation. It is simulator-agnostic, working with major simulators like Verilator, ModelSim, VCS, Xcelium, GHDL, and Icarus Verilog.

## Use cases
- write RTL testbenches in Python instead of SystemVerilog
- verify VHDL and Verilog chip designs with a Python testbench
- run hardware simulation tests in CI pipelines
- replace UVM with a Python-based verification workflow
- test mixed-language or mixed-signal designs with one framework
- drive a Verilator or Icarus Verilog simulation from Python coroutines

## When to choose
- you want to verify RTL designs using Python and its ecosystem instead of HDL testbench languages
- you need simulator-agnostic verification across multiple commercial and open-source simulators
- your team is more productive in Python than in SystemVerilog/UVM
- you want easy CI integration for hardware regression testing

## When to avoid
- you need formal verification or static property checking rather than simulation
- your team and existing infrastructure are fully committed to UVM/SystemVerilog methodologies
- you require cycle-accurate synthesis-level performance from the testbench itself
- your simulator is not among the supported cosimulation targets

## Facets
- artifact type: framework
- maturity: stable
- function: testing, simulation, developer-tools
- domain: hardware, embedded-systems, developer-tools, testing
- platform: windows, python, cross-platform
- tags: rtl-verification, testbench, vhdl, verilog, systemverilog, cosimulation, hardware-verification, chip-design, uvm-alternative, linux, macos

## Member repositories
- cocotb/cocotb (main) score 73

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:55.447575+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:28:06.017575+00:00, confidence not recorded.
  - readme: https://github.com/cocotb/cocotb (fetched 2026-08-28T04:06:55.447575+00:00, sha 3d35c383c48a)
  - homepage: https://www.cocotb.org (fetched 2026-08-29T10:11:45.329842+00:00, sha e03bfbf5db20)
- Data as of 2026-08-30T08:39:29.467469+00:00.