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clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler observed · 2026-08-28

github.com/clash-lang/clash-compiler · homepage · Haskell · NOASSERTION (other) observed · 2026-08-28

Health v2 · maintenance only

88/100

  • Activity 99
  • Release rhythm 68
  • Longevity 100

Flags: no_license

How is this computed?

round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10) — computed 2026-09-03. Adoption (stars, forks) is never an input.

  • gap_med: 84.5
  • age_days: 4808
  • days_rel: 132
  • days_push: 7
  • n_releases_24m: 5

Full methodology

Adoption not part of the score

1606 stars · 169 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Clash is a functional hardware description language based on Haskell, with a compiler that transforms high-level descriptions into synthesizable VHDL, Verilog, or SystemVerilog. It offers strong typing, type inference, an interactive REPL, and type-safe multi-clock-domain design for FPGA and ASIC development.

Use cases

  • write FPGA designs in Haskell instead of VHDL or Verilog
  • compile Haskell-like hardware descriptions to synthesizable VHDL, Verilog, or SystemVerilog
  • prototype digital circuits interactively in a REPL without writing test benches
  • design synchronous sequential circuits with type-safe clock domain crossing
  • build parametric, reusable hardware components using higher-order functions
  • implement CPUs and retro-computing devices on FPGAs
  • verify hardware designs with strong static typing

When to choose

  • you know Haskell and want to do FPGA or ASIC hardware design
  • you want strongly typed, high-level hardware descriptions that compile to standard HDLs
  • you need rapid prototyping of digital circuits with an interactive REPL
  • you want reusable, parametric hardware designs via functional abstractions
  • you need type-safe clock domain crossing in multi-clock designs

When to avoid

  • your team only knows traditional HDLs like VHDL or Verilog and has no Haskell experience
  • you need fine-grained low-level control over every hardware primitive
  • your toolchain or vendor flow does not accept generated VHDL/Verilog/SystemVerilog
  • you need a large ecosystem of off-the-shelf IP cores written in Clash

Facets

cli-tool · maturity active

compiler programming-language simulation testing hardware embedded-systems programming-languages compilers windows cross-platform haskell hardware-description-language fpga vhdl verilog systemverilog asic synthesizable-hardware functional-programming compiler linux macos

4 sources

Member repositories

RepositoryRoleHealth v2
clash-lang/clash-compilermain88

For agents

markdown · JSON · MCP: product_card(name="clash-lang/clash-compiler")

Data as of 2026-08-30T08:39:29.467469+00:00 · Report a problem