# clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Repository: https://github.com/clash-lang/clash-compiler
Canonical: https://ross.abutalabs.com/products/clash-compiler
Homepage: https://clash-lang.org/
Language: Haskell
License: NOASSERTION
License Family: other
Topics: haskell, hardware-description-language, fpga, vhdl, verilog, systemverilog, asic
Last push: 2026-08-26T19:12:16+00:00

## Health v2 (maintenance only)
Score: 88/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 68, longevity 100
- inputs: {"age_days": 4808, "days_push": 7, "days_rel": 132, "gap_med": 84.5, "n_releases_24m": 5}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1606, forks 169 (observed 2026-08-28T04:05:10.528134+00:00)

## What it is
Clash is a functional hardware description language based on Haskell, with a compiler that transforms high-level descriptions into synthesizable VHDL, Verilog, or SystemVerilog. It offers strong typing, type inference, an interactive REPL, and type-safe multi-clock-domain design for FPGA and ASIC development.

## Use cases
- write FPGA designs in Haskell instead of VHDL or Verilog
- compile Haskell-like hardware descriptions to synthesizable VHDL, Verilog, or SystemVerilog
- prototype digital circuits interactively in a REPL without writing test benches
- design synchronous sequential circuits with type-safe clock domain crossing
- build parametric, reusable hardware components using higher-order functions
- implement CPUs and retro-computing devices on FPGAs
- verify hardware designs with strong static typing

## When to choose
- you know Haskell and want to do FPGA or ASIC hardware design
- you want strongly typed, high-level hardware descriptions that compile to standard HDLs
- you need rapid prototyping of digital circuits with an interactive REPL
- you want reusable, parametric hardware designs via functional abstractions
- you need type-safe clock domain crossing in multi-clock designs

## When to avoid
- your team only knows traditional HDLs like VHDL or Verilog and has no Haskell experience
- you need fine-grained low-level control over every hardware primitive
- your toolchain or vendor flow does not accept generated VHDL/Verilog/SystemVerilog
- you need a large ecosystem of off-the-shelf IP cores written in Clash

## Facets
- artifact type: cli-tool
- maturity: active
- function: compiler, programming-language, simulation, testing
- domain: hardware, embedded-systems, programming-languages, compilers
- platform: windows, cross-platform
- tags: haskell, hardware-description-language, fpga, vhdl, verilog, systemverilog, asic, synthesizable-hardware, functional-programming, compiler, linux, macos

## Member repositories
- clash-lang/clash-compiler (main) score 88

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:10.528134+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T08:32:42.574165+00:00, confidence not recorded.
  - readme: https://github.com/clash-lang/clash-compiler (fetched 2026-08-28T04:05:10.528134+00:00, sha f911d87d7839)
  - homepage: https://clash-lang.org/ (fetched 2026-08-29T11:23:48.256861+00:00, sha d80dde0a8877)
  - site_page: https://clash-lang.org/documentation (fetched 2026-08-29T11:23:48.263766+00:00, sha df6a56213152)
  - site_page: https://clash-lang.org/install (fetched 2026-08-29T11:23:48.265906+00:00, sha 4e1d8c6091b7)
- Data as of 2026-08-30T08:39:29.467469+00:00.