ucb-bar/chipyard

Health v2 · maintenance only

Adoption not part of the score

2366 stars · 904 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Chipyard is an open-source agile hardware design framework for building Chisel-based RISC-V systems-on-chip, including processor cores (Rocket, BOOM, CVA6), vector units, and custom accelerators. It integrates RTL simulation, FPGA-accelerated simulation via FireSim, automated VLSI flows via Hammer, and workload generation via FireMarshal.

Use cases

• generate a custom RISC-V SoC with peripherals and accelerators
• simulate a RISC-V chip design in RTL or on FPGA
• design a custom accelerator and integrate it into an SoC
• run VLSI implementation flows on a generated SoC
• build bare-metal or Linux workloads for a custom RISC-V core
• evaluate out-of-order core designs like BOOM

When to choose

• you are doing computer architecture research on RISC-V processors or SoCs
• you need an agile, generator-based hardware design flow from RTL to tapeout
• you want FPGA-accelerated simulation of full SoC designs
• you need pre-integrated cores, vector units, and accelerators like Gemmini

When to avoid

• you need a production embedded SDK or off-the-shelf microcontroller
• you work with non-RISC-V or non-Chisel hardware designs
• you want a lightweight HDL simulator without SoC generation
• you lack the compute resources or expertise for heavy hardware build flows

Facets

framework · maturity active

simulation compiler developer-tools embedded hardware cli risc-v soc-design chisel rocket-chip fpga-simulation vlsi hardware-generation accelerators boom firesim computer-architecture research linux docker

Member repositories

For agents

markdown · JSON · MCP: product_card(name="ucb-bar/chipyard")