# ucb-bar/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Repository: https://github.com/ucb-bar/chipyard
Canonical: https://ross.abutalabs.com/products/chipyard
Homepage: https://chipyard.readthedocs.io/en/latest/
Language: Scala
License: BSD-3-Clause
License Family: permissive
Topics: rocket-chip, chip-generator, chisel, riscv, rtl, soc, peripherals, chipyard, risc-v, boom, firesim, hwacha, accelerators, rocket, out-of-order, superscalar
Last push: 2026-08-19T06:11:29+00:00

## Health v2 (maintenance only)
Score: 84/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 98, release rhythm 57, longevity 100
- inputs: {"age_days": 3600, "days_push": 14, "days_rel": 73, "gap_med": 629, "n_releases_24m": 2}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2366, forks 904 (observed 2026-08-28T04:06:41.561370+00:00)

## What it is
Chipyard is an open-source agile hardware design framework for building Chisel-based RISC-V systems-on-chip, including processor cores (Rocket, BOOM, CVA6), vector units, and custom accelerators. It integrates RTL simulation, FPGA-accelerated simulation via FireSim, automated VLSI flows via Hammer, and workload generation via FireMarshal.

## Use cases
- generate a custom RISC-V SoC with peripherals and accelerators
- simulate a RISC-V chip design in RTL or on FPGA
- design a custom accelerator and integrate it into an SoC
- run VLSI implementation flows on a generated SoC
- build bare-metal or Linux workloads for a custom RISC-V core
- evaluate out-of-order core designs like BOOM

## When to choose
- you are doing computer architecture research on RISC-V processors or SoCs
- you need an agile, generator-based hardware design flow from RTL to tapeout
- you want FPGA-accelerated simulation of full SoC designs
- you need pre-integrated cores, vector units, and accelerators like Gemmini

## When to avoid
- you need a production embedded SDK or off-the-shelf microcontroller
- you work with non-RISC-V or non-Chisel hardware designs
- you want a lightweight HDL simulator without SoC generation
- you lack the compute resources or expertise for heavy hardware build flows

## Facets
- artifact type: framework
- maturity: active
- function: simulation, compiler, developer-tools, embedded
- domain: hardware
- platform: cli
- tags: risc-v, soc-design, chisel, rocket-chip, fpga-simulation, vlsi, hardware-generation, accelerators, boom, firesim, computer-architecture, research, linux, docker

## Member repositories
- ucb-bar/chipyard (main) score 84

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:41.561370+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:35:58.875507+00:00, confidence not recorded.
  - readme: https://github.com/ucb-bar/chipyard (fetched 2026-08-28T04:06:41.561370+00:00, sha 3cd24e0a8da5)
- Data as of 2026-08-30T08:39:29.467469+00:00.