ultraembedded/biriscv

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

1292 stars · 202 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

biRISC-V is a 32-bit superscalar (dual-issue) in-order RISC-V CPU core written in synthesizable Verilog 2001, supporting RV32IMZicsr with branch prediction, caches, and MMU capable of booting Linux. It targets both FPGA (e.g., Xilinx Artix-7) and ASIC synthesis, verified with RISCV-DV and cosimulation against a C++ ISA model.

Use cases

• open-source RISC-V CPU core for FPGA projects
• boot Linux on a soft core on a cheap hobbyist FPGA
• learn how superscalar dual-issue pipelines and branch prediction work
• integrate a RISC-V core into an ASIC design
• simulate a RISC-V CPU with Verilator
• compare open RISC-V cores against SiFive E76 or WD SweRV

When to choose

• you need an open-source, Linux-capable RV32 core that fits a small FPGA
• you want readable Verilog 2001 you can modify and learn from
• you need competitive CoreMark performance for an in-order core
• you want FPGA-friendly caches, TCM, and AXI interface options

When to avoid

• you need RV64 or out-of-order execution
• you need hardware atomics (A extension is emulated in software)
• you need a commercial-grade core with support and guarantees
• you need floating point (F/D) or compressed (C) instruction support

Facets

library · maturity maintenance

embedded simulation hardware embedded-systems operating-systems risc-v cpu-core superscalar dual-issue branch-prediction fpga asic verilator rv32im coremark open-source-hardware verilog xilinx linux

Member repositories

For agents

markdown · JSON · MCP: product_card(name="ultraembedded/biriscv")