# ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

Repository: https://github.com/ultraembedded/biriscv
Canonical: https://ross.abutalabs.com/products/biriscv
Language: Verilog
License: Apache-2.0
License Family: permissive
Topics: risc-v, rv32i, rv32im, superscalar, cpu, fpga, verilog, pipelined-processors, verilator, coremark, asic, branch-prediction, in-order, linux, riscv-linux, xilinx, artix-7
Last push: 2021-09-18T17:41:41+00:00

## Health v2 (maintenance only)
Score: 32/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 0, release rhythm 35, longevity 100
- inputs: {"age_days": 2396, "days_push": 1810, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1292, forks 202 (observed 2026-08-28T04:04:16.013470+00:00)

## What it is
biRISC-V is a 32-bit superscalar (dual-issue) in-order RISC-V CPU core written in synthesizable Verilog 2001, supporting RV32IMZicsr with branch prediction, caches, and MMU capable of booting Linux. It targets both FPGA (e.g., Xilinx Artix-7) and ASIC synthesis, verified with RISCV-DV and cosimulation against a C++ ISA model.

## Use cases
- open-source RISC-V CPU core for FPGA projects
- boot Linux on a soft core on a cheap hobbyist FPGA
- learn how superscalar dual-issue pipelines and branch prediction work
- integrate a RISC-V core into an ASIC design
- simulate a RISC-V CPU with Verilator
- compare open RISC-V cores against SiFive E76 or WD SweRV

## When to choose
- you need an open-source, Linux-capable RV32 core that fits a small FPGA
- you want readable Verilog 2001 you can modify and learn from
- you need competitive CoreMark performance for an in-order core
- you want FPGA-friendly caches, TCM, and AXI interface options

## When to avoid
- you need RV64 or out-of-order execution
- you need hardware atomics (A extension is emulated in software)
- you need a commercial-grade core with support and guarantees
- you need floating point (F/D) or compressed (C) instruction support

## Facets
- artifact type: library
- maturity: maintenance
- function: embedded, simulation
- domain: hardware, embedded-systems, operating-systems
- platform: -
- tags: risc-v, cpu-core, superscalar, dual-issue, branch-prediction, fpga, asic, verilator, rv32im, coremark, open-source-hardware, verilog, xilinx, linux

## Member repositories
- ultraembedded/biriscv (main) score 32

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:16.013470+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T04:54:45.478317+00:00, confidence not recorded.
  - readme: https://github.com/ultraembedded/biriscv (fetched 2026-08-28T04:04:16.013470+00:00, sha bbedd06089ec)
- Data as of 2026-08-30T08:39:29.467469+00:00.