YosysHQ/yosys

Health v2 · maintenance only

Adoption not part of the score

4704 stars · 1149 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

Yosys is an open-source framework for Verilog/SystemVerilog RTL synthesis, converting hardware description code into gate-level netlists for ASICs and FPGAs. It is scriptable, extensible via C++ passes, and serves as the foundation for many open-source EDA flows including formal verification tools like SBY.

Use cases

• synthesize Verilog to a gate-level netlist for an ASIC standard cell library
• map an RTL design to Lattice iCE40, ECP5, or Xilinx 7-Series FPGAs
• convert Verilog to BLIF, EDIF, BTOR, or SMT-LIB formats
• check equivalence or properties of hardware designs with formal methods
• build a custom synthesis flow on an extensible open-source framework
• elaborate and analyze a synthesizable SystemVerilog design

When to choose

• you need a free, open-source RTL synthesis tool for FPGA or ASIC flows
• you want a scriptable, extensible synthesis framework for research or custom toolchains
• you need a front-end for formal hardware verification with SMT solvers

When to avoid

• you require industry-grade VHDL or full SystemVerilog assertion support without a commercial license
• you need place-and-route or bitstream generation - pair it with nextpnr or vendor tools
• you want a GUI-driven EDA suite rather than a command-line script-based tool

Facets

framework · maturity stable

compiler developer-tools simulation parser hardware embedded-systems developer-tools compilers windows cpp cli rtl-synthesis verilog systemverilog fpga asic netlist formal-verification hardware-description-language open-source-eda linux macos

Member repositories

For agents

markdown · JSON · MCP: product_card(name="YosysHQ/yosys")