# YosysHQ/yosys

Yosys Open SYnthesis Suite

Repository: https://github.com/YosysHQ/yosys
Canonical: https://ross.abutalabs.com/products/yosys
Homepage: https://yosyshq.net/yosys/
Language: C++
License: ISC
License Family: permissive
Last push: 2026-08-26T15:39:52+00:00

## Health v2 (maintenance only)
Score: 98/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 99, release rhythm 96, longevity 100
- inputs: {"age_days": 4988, "days_push": 7, "days_rel": 28, "gap_med": 28.5, "n_releases_24m": 25}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 4704, forks 1149 (observed 2026-08-28T04:08:57.242852+00:00)

## What it is
Yosys is an open-source framework for Verilog/SystemVerilog RTL synthesis, converting hardware description code into gate-level netlists for ASICs and FPGAs. It is scriptable, extensible via C++ passes, and serves as the foundation for many open-source EDA flows including formal verification tools like SBY.

## Use cases
- synthesize Verilog to a gate-level netlist for an ASIC standard cell library
- map an RTL design to Lattice iCE40, ECP5, or Xilinx 7-Series FPGAs
- convert Verilog to BLIF, EDIF, BTOR, or SMT-LIB formats
- check equivalence or properties of hardware designs with formal methods
- build a custom synthesis flow on an extensible open-source framework
- elaborate and analyze a synthesizable SystemVerilog design

## When to choose
- you need a free, open-source RTL synthesis tool for FPGA or ASIC flows
- you want a scriptable, extensible synthesis framework for research or custom toolchains
- you need a front-end for formal hardware verification with SMT solvers

## When to avoid
- you require industry-grade VHDL or full SystemVerilog assertion support without a commercial license
- you need place-and-route or bitstream generation - pair it with nextpnr or vendor tools
- you want a GUI-driven EDA suite rather than a command-line script-based tool

## Facets
- artifact type: framework
- maturity: stable
- function: compiler, developer-tools, simulation, parser
- domain: hardware, embedded-systems, developer-tools, compilers
- platform: windows, cpp, cli
- tags: rtl-synthesis, verilog, systemverilog, fpga, asic, netlist, formal-verification, hardware-description-language, open-source-eda, linux, macos

## Member repositories
- YosysHQ/yosys (main) score 98

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:08:57.242852+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:19:11.587755+00:00, confidence not recorded.
  - readme: https://github.com/YosysHQ/yosys (fetched 2026-08-28T04:08:57.242852+00:00, sha 291abb70d0e8)
  - homepage: https://yosyshq.net/yosys/ (fetched 2026-08-29T09:03:04.592163+00:00, sha 3e0c2a923acb)
  - site_page: https://yosyshq.net/yosys/about.html (fetched 2026-08-29T09:03:04.595103+00:00, sha 3e0c2a923acb)
  - site_page: https://yosyshq.net/yosys/documentation.html (fetched 2026-08-29T09:03:04.597045+00:00, sha a7ffb7f1da1c)
- Data as of 2026-08-30T08:39:29.467469+00:00.