OpenXiangShan/XiangShan

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

7213 stars · 935 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

XiangShan is an open-source high-performance RISC-V processor core written in Chisel (Scala). It serves as both an industrial-grade CPU design and a research platform for microarchitecture innovation using agile development methodology.

Use cases

• designing a high-performance out-of-order RISC-V CPU
• researching novel microarchitectures for processors
• learning how a modern out-of-order processor is built
• taping out an open-source RISC-V chip
• exploring agile hardware development flows with Chisel
• running RISC-V software on an open-source core

When to choose

• you need an open, high-performance RISC-V processor design you can modify
• you want a research vehicle for CPU microarchitecture experiments
• you prefer Chisel-based agile hardware development
• you need an industrial-strength alternative to academic toy cores

When to avoid

• you need a small, simple embedded RISC-V core (use Rocket or PicoRV32 instead)
• you cannot afford the compute resources for simulation and verification
• you need a soft core for low-end FPGAs with limited resources
• you require a mature silicon-proven design with long-term vendor support

Facets

library · maturity active

simulation compiler hardware jvm risc-v processor-design chisel cpu microarchitecture open-hardware hdl processors research linux fpga asic

Member repositories

For agents

markdown · JSON · MCP: product_card(name="OpenXiangShan/XiangShan")