# OpenXiangShan/XiangShan

Open-source high-performance RISC-V processor

Repository: https://github.com/OpenXiangShan/XiangShan
Canonical: https://ross.abutalabs.com/products/xiangshan
Homepage: https://xiangshan.cc
Language: Scala
License: MulanPSL-2.0
License Family: other
Topics: risc-v, microarchitecture, chisel
Last push: 2026-08-26T19:10:37+00:00

## Health v2 (maintenance only)
Score: 77/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 35, longevity 100
- inputs: {"age_days": 2272, "days_push": 7, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 7213, forks 935 (observed 2026-08-28T04:09:57.525238+00:00)

## What it is
XiangShan is an open-source high-performance RISC-V processor core written in Chisel (Scala). It serves as both an industrial-grade CPU design and a research platform for microarchitecture innovation using agile development methodology.

## Use cases
- designing a high-performance out-of-order RISC-V CPU
- researching novel microarchitectures for processors
- learning how a modern out-of-order processor is built
- taping out an open-source RISC-V chip
- exploring agile hardware development flows with Chisel
- running RISC-V software on an open-source core

## When to choose
- you need an open, high-performance RISC-V processor design you can modify
- you want a research vehicle for CPU microarchitecture experiments
- you prefer Chisel-based agile hardware development
- you need an industrial-strength alternative to academic toy cores

## When to avoid
- you need a small, simple embedded RISC-V core (use Rocket or PicoRV32 instead)
- you cannot afford the compute resources for simulation and verification
- you need a soft core for low-end FPGAs with limited resources
- you require a mature silicon-proven design with long-term vendor support

## Facets
- artifact type: library
- maturity: active
- function: simulation, compiler
- domain: hardware
- platform: jvm
- tags: risc-v, processor-design, chisel, cpu, microarchitecture, open-hardware, hdl, processors, research, linux, fpga, asic

## Member repositories
- OpenXiangShan/XiangShan (main) score 77

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:09:57.525238+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T17:39:49.691725+00:00, confidence not recorded.
  - readme: https://github.com/OpenXiangShan/XiangShan (fetched 2026-08-28T04:09:57.525238+00:00, sha 29d2b094db82)
  - homepage: https://xiangshan.cc (fetched 2026-08-29T08:34:44.092650+00:00, sha 9fdb3c1dbb49)
- Data as of 2026-08-30T08:39:29.467469+00:00.