chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum! observed · 2026-08-28
Health v2 · maintenance only
68/100
- Activity 99
- Release rhythm 36
- Longevity 55
How is this computed?
round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10) — computed 2026-09-03. Adoption (stars, forks) is never an input.
- gap_med: n/a
- age_days: 781
- days_rel: 218
- days_push: 7
- n_releases_24m: 1
Adoption not part of the score
1355 stars · 35 forks observed · 2026-08-28
What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded
An open-source, wire-speed hardware implementation of the WireGuard VPN protocol on a low-cost Artix-7 FPGA, written in Verilog with an open-source toolchain (OpenXC7, Verilator, cocotb). It builds a complete hardware-software SoC including a RISC-V CPU and open Ethernet IP for secure, high-throughput tunneling.
Use cases
- implement wireguard vpn in hardware on an fpga
- line-rate encrypted vpn tunneling beyond software performance
- open-source verilog wireguard gateware for security auditing
- learn fpga networking and rtl design with a real project
- build a low-cost hardware vpn appliance with 1g ethernet ports
- verify no backdoors in a vpn implementation via open rtl
When to choose
- you need wireguard throughput that software implementations cannot reach
- you require a fully open, auditable hardware VPN stack with no proprietary IP blocks
- you want an affordable FPGA platform (Artix-7) supported by open-source tooling
- you are studying or teaching hardware security and RTL networking
When to avoid
- you just need a working VPN on general-purpose hardware - use standard WireGuard software
- you need a turnkey product with vendor support or certification
- you lack FPGA hardware or interest in working with HDL toolchains
- you need multi-100G throughput like the proprietary Alveo-based solutions
Facets
library · maturity active
vpn cryptography networking security embedded security networking privacy hardware embedded-systems embedded self-hosted wireguard fpga verilog risc-v rtl cocotb verilator open-source-hardware artix-7 nlnet linux
2 sources
- readme: https://github.com/chili-chips-ba/wireguard-fpga · fetched 2026-08-28 · 6b2fe4be5877
- homepage: https://nlnet.nl/project/KlusterLab-Wireguard · fetched 2026-08-29 · 2b47fb3736e6
Member repositories
| Repository | Role | Health v2 |
|---|---|---|
| chili-chips-ba/wireguard-fpga | main | 68 |
For agents
markdown · JSON · MCP: product_card(name="chili-chips-ba/wireguard-fpga")
Data as of 2026-08-30T08:39:29.467469+00:00 · Report a problem