chipsalliance/verible

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

1918 stars · 301 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Verible is a suite of SystemVerilog (IEEE 1800-2017) developer tools built in C++, including a parser, style linter, formatter, and Language Server Protocol implementation. It aims to eliminate the need for anyone to write their own SystemVerilog parser by providing reusable, standard-compliant parsing components.

Use cases

• parse SystemVerilog files and export syntax trees as JSON
• lint SystemVerilog code against a style guide
• format SystemVerilog source files
• add SystemVerilog language support to editors via LSP
• analyze un-preprocessed SystemVerilog source in custom tools
• visualize SystemVerilog syntax structure for debugging

When to choose

• you need a standard-compliant SystemVerilog parser without building one yourself
• you want automated style checking or formatting for SystemVerilog codebases
• you are building editor or IDE tooling for SystemVerilog
• you need to extract syntax trees from HDL code for analysis

When to avoid

• you need a full preprocessed compilation flow like a synthesis tool or simulator
• you work with VHDL or other HDLs rather than SystemVerilog
• you need elaboration or type checking, which Verible does not provide

Facets

cli-tool · maturity active

parser linter formatter developer-tools developer-tools hardware parsers windows cli systemverilog language-server lsp syntax-tree fpga hdl code-analysis linux macos

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