# chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Repository: https://github.com/chipsalliance/verible
Canonical: https://ross.abutalabs.com/products/verible
Homepage: https://chipsalliance.github.io/verible/
Language: C++
License: NOASSERTION
License Family: other
Topics: systemverilog, lexer, yacc, syntax-tree, linter, formatter, parser, systemverilog-parser, style-linter, hacktoberfest, productivity, analysis, systemverilog-developer, sv-lrm, verible, language-server-protocol, lsp-server
Last push: 2026-08-16T07:23:14+00:00

## Health v2 (maintenance only)
Score: 94/100 (v2, computed 2026-09-03T02:39:23.370411+00:00)
- activity 98, release rhythm 86, longevity 100
- inputs: {"age_days": 2492, "days_push": 17, "days_rel": 17, "gap_med": 1, "n_releases_24m": 112}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1918, forks 301 (observed 2026-08-28T04:05:54.893235+00:00)

## What it is
Verible is a suite of SystemVerilog (IEEE 1800-2017) developer tools built in C++, including a parser, style linter, formatter, and Language Server Protocol implementation. It aims to eliminate the need for anyone to write their own SystemVerilog parser by providing reusable, standard-compliant parsing components.

## Use cases
- parse SystemVerilog files and export syntax trees as JSON
- lint SystemVerilog code against a style guide
- format SystemVerilog source files
- add SystemVerilog language support to editors via LSP
- analyze un-preprocessed SystemVerilog source in custom tools
- visualize SystemVerilog syntax structure for debugging

## When to choose
- you need a standard-compliant SystemVerilog parser without building one yourself
- you want automated style checking or formatting for SystemVerilog codebases
- you are building editor or IDE tooling for SystemVerilog
- you need to extract syntax trees from HDL code for analysis

## When to avoid
- you need a full preprocessed compilation flow like a synthesis tool or simulator
- you work with VHDL or other HDLs rather than SystemVerilog
- you need elaboration or type checking, which Verible does not provide

## Facets
- artifact type: cli-tool
- maturity: active
- function: parser, linter, formatter, developer-tools
- domain: developer-tools, hardware, parsers
- platform: windows, cli
- tags: systemverilog, language-server, lsp, syntax-tree, fpga, hdl, code-analysis, linux, macos

## Member repositories
- chipsalliance/verible (main) score 94

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:54.893235+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:09:59.644192+00:00, confidence not recorded.
  - readme: https://github.com/chipsalliance/verible (fetched 2026-08-28T04:05:54.893235+00:00, sha 0abc5f44cfc2)
  - homepage: https://chipsalliance.github.io/verible/ (fetched 2026-08-29T10:49:17.385537+00:00, sha 74e9be826083)
- Data as of 2026-08-30T08:39:29.467469+00:00.