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siliconcompiler/siliconcompiler

Modular hardware build system observed · 2026-09-03

github.com/siliconcompiler/siliconcompiler · homepage · Python · Apache-2.0 (permissive) observed · 2026-09-03

Health v2 · maintenance only

100/100

  • Activity 100
  • Release rhythm 100
  • Longevity 100
How is this computed?

round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10) — computed 2026-09-03. Adoption (stars, forks) is never an input.

  • gap_med: 10
  • age_days: 2092
  • days_rel: 0
  • days_push: 0
  • n_releases_24m: 60

Full methodology

Adoption not part of the score

1206 stars · 136 forks observed · 2026-09-03

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

SiliconCompiler is a modular Python-based hardware build system that automates the flow from RTL source code (Verilog, VHDL, Chisel, etc.) through synthesis, place-and-route, and verification to GDSII, supporting both ASIC and FPGA targets. It orchestrates open-source and commercial EDA tools (Yosys, OpenROAD, Verilator, Vivado, Cadence, Synopsys) with pluggable PDKs, flows, and remote/cloud execution.

Use cases

  • compile RTL to GDS for an ASIC
  • build an FPGA bitstream from Verilog
  • automate my chip design flow instead of makefiles
  • run synthesis and place-and-route with open source tools
  • lint my Verilog without installing EDA tools
  • run hardware builds in CI on every commit
  • try ASIC compilation in the cloud without installing tools
  • simulate my design with Verilator or Icarus

When to choose

  • you want a scriptable, Python-based alternative to hand-written Makefiles for chip or FPGA builds
  • you need to mix open-source and commercial EDA tools in one automated flow
  • you want to try hardware compilation quickly via remote execution or Docker without installing EDA tools
  • you need reproducible, CI-friendly hardware builds with packaged PDKs like sky130 or gf180

When to avoid

  • you need a GUI-driven EDA workflow with interactive layout editing
  • your flow depends on proprietary foundry PDKs you cannot package or share
  • you only need simple FPGA synthesis where vendor IDEs (Vivado, Quartus) already suffice
  • you work primarily on Windows with local tool execution, which is unsupported

Facets

framework · maturity active

build-tool compiler workflow-automation developer-tools ci-cd hardware embedded-systems developer-tools cross-platform windows python cloud cli eda asic fpga rtl-to-gds verilog vhdl synthesis place-and-route openroad yosys pdk hardware-build-system make-for-silicon automation linux macos docker

7 sources

Member repositories

RepositoryRoleHealth v2
siliconcompiler/siliconcompilermain100

For agents

markdown · JSON · MCP: product_card(name="siliconcompiler/siliconcompiler")

Data as of 2026-08-30T08:39:29.467469+00:00 · Report a problem