sifive/freedom

Health v2 · maintenance only

Flags: archived

Adoption not part of the score

1147 stars · 280 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

SiFive's Freedom platform RTL source files, written in Chisel (Scala), implementing the Freedom E300 and U500 RISC-V SoC platforms for FPGA dev kits (Arty and VC707). It generates Verilog for building RISC-V systems on FPGAs. The repository was archived by SiFive on March 1, 2021 and is no longer actively maintained.

Use cases

• build a RISC-V SoC on an Arty FPGA board
• generate Verilog from Chisel for the Freedom E300 platform
• implement the Freedom U500 platform on a VC707 FPGA
• study SiFive's RISC-V SoC RTL design
• boot a RISC-V system on FPGA with an external debugger

When to choose

• you need the original SiFive Freedom E300/U500 RTL for an Arty or VC707 FPGA dev kit
• you want to study or fork a Chisel-based RISC-V SoC implementation
• you are working with legacy SiFive FPGA tooling and matching dependencies

When to avoid

• you need actively maintained RISC-V SoC generators (consider newer forks or Chipyard)
• you target modern FPGA boards or current software ecosystems
• you want production-supported silicon or up-to-date toolchain compatibility

Facets

library · maturity abandoned

simulation compiler embedded-systems hardware developer-tools risc-v chisel fpga soc rtl sifive scala verilog-generation linux

Member repositories

For agents

markdown · JSON · MCP: product_card(name="sifive/freedom")