# sifive/freedom

Source files for SiFive's Freedom platforms

Repository: https://github.com/sifive/freedom
Canonical: https://ross.abutalabs.com/products/sifive-freedom
Language: Scala
License: Apache-2.0
License Family: permissive
Archived: true
Last push: 2026-07-17T18:54:09+00:00

## Health v2 (maintenance only)
Score: 10/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 93, release rhythm 8, longevity 100
- inputs: {"age_days": 3570, "days_push": 47, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: archived
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1147, forks 280 (observed 2026-08-28T04:03:45.989823+00:00)

## What it is
SiFive's Freedom platform RTL source files, written in Chisel (Scala), implementing the Freedom E300 and U500 RISC-V SoC platforms for FPGA dev kits (Arty and VC707). It generates Verilog for building RISC-V systems on FPGAs. The repository was archived by SiFive on March 1, 2021 and is no longer actively maintained.

## Use cases
- build a RISC-V SoC on an Arty FPGA board
- generate Verilog from Chisel for the Freedom E300 platform
- implement the Freedom U500 platform on a VC707 FPGA
- study SiFive's RISC-V SoC RTL design
- boot a RISC-V system on FPGA with an external debugger

## When to choose
- you need the original SiFive Freedom E300/U500 RTL for an Arty or VC707 FPGA dev kit
- you want to study or fork a Chisel-based RISC-V SoC implementation
- you are working with legacy SiFive FPGA tooling and matching dependencies

## When to avoid
- you need actively maintained RISC-V SoC generators (consider newer forks or Chipyard)
- you target modern FPGA boards or current software ecosystems
- you want production-supported silicon or up-to-date toolchain compatibility

## Facets
- artifact type: library
- maturity: abandoned
- function: simulation, compiler
- domain: embedded-systems, hardware, developer-tools
- platform: -
- tags: risc-v, chisel, fpga, soc, rtl, sifive, scala, verilog-generation, linux

## Member repositories
- sifive/freedom (main) score 10

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:45.989823+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:34:03.771681+00:00, confidence not recorded.
  - readme: https://github.com/sifive/freedom (fetched 2026-08-28T04:03:45.989823+00:00, sha 1d62b534aa1c)
- Data as of 2026-08-30T08:39:29.467469+00:00.