chipsalliance/rocket-chip

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

3849 stars · 1289 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

Rocket Chip is a Scala/Chisel-based hardware generator that produces parameterizable RISC-V System-on-Chip designs, emitting Verilog RTL for the Rocket core and its surrounding SoC. It is maintained under CHIPS Alliance and supports simulation with Verilator, FPGA mapping, and ASIC VLSI flows.

Use cases

• generate a parameterizable RISC-V SoC in Verilog
• simulate a Rocket core with Verilator
• map a RISC-V core onto an FPGA
• customize a Rocket chip configuration for ASIC tapeout
• learn Chisel-based hardware design

When to choose

• you need a production-quality, open-source RISC-V core generator
• you want to parameterize a SoC (cache sizes, cores, peripherals) in Scala/Chisel
• you are doing research or education on RISC-V hardware

When to avoid

• you need a fixed, pre-built processor binary rather than RTL generation
• you are not comfortable with Scala, Chisel, and FPGA/ASIC toolchains
• you need a soft core for a non-RISC-V ISA

Facets

library · maturity active

compiler simulation developer-tools hardware embedded-systems operating-systems cli riscv chisel rtl chip-design fpga verilog scala soc hardware-generator linux macos

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markdown · JSON · MCP: product_card(name="chipsalliance/rocket-chip")