# chipsalliance/rocket-chip

Rocket Chip Generator

Repository: https://github.com/chipsalliance/rocket-chip
Canonical: https://ross.abutalabs.com/products/rocket-chip
Language: Scala
License: NOASSERTION
License Family: other
Topics: scala, rocket-chip, chip-generator, chisel, riscv, rtl
Last push: 2026-06-02T17:57:09+00:00

## Health v2 (maintenance only)
Score: 61/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 85, release rhythm 8, longevity 100
- inputs: {"age_days": 4373, "days_push": 92, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3849, forks 1289 (observed 2026-08-28T04:08:24.239771+00:00)

## What it is
Rocket Chip is a Scala/Chisel-based hardware generator that produces parameterizable RISC-V System-on-Chip designs, emitting Verilog RTL for the Rocket core and its surrounding SoC. It is maintained under CHIPS Alliance and supports simulation with Verilator, FPGA mapping, and ASIC VLSI flows.

## Use cases
- generate a parameterizable RISC-V SoC in Verilog
- simulate a Rocket core with Verilator
- map a RISC-V core onto an FPGA
- customize a Rocket chip configuration for ASIC tapeout
- learn Chisel-based hardware design

## When to choose
- you need a production-quality, open-source RISC-V core generator
- you want to parameterize a SoC (cache sizes, cores, peripherals) in Scala/Chisel
- you are doing research or education on RISC-V hardware

## When to avoid
- you need a fixed, pre-built processor binary rather than RTL generation
- you are not comfortable with Scala, Chisel, and FPGA/ASIC toolchains
- you need a soft core for a non-RISC-V ISA

## Facets
- artifact type: library
- maturity: active
- function: compiler, simulation, developer-tools
- domain: hardware, embedded-systems, operating-systems
- platform: cli
- tags: riscv, chisel, rtl, chip-design, fpga, verilog, scala, soc, hardware-generator, linux, macos

## Member repositories
- chipsalliance/rocket-chip (main) score 61

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:08:24.239771+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:25:58.762451+00:00, confidence not recorded.
  - readme: https://github.com/chipsalliance/rocket-chip (fetched 2026-08-28T04:08:24.239771+00:00, sha a833f3b21ed4)
- Data as of 2026-08-30T08:39:29.467469+00:00.