riscv-software-src/riscv-tests

Health v2 · maintenance only

Flags: no_releases no_license

Adoption not part of the score

1236 stars · 562 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

The official unit test suite for RISC-V processor implementations, written mostly in assembly. Tests are organized by test virtual machines (TVMs) covering user- and supervisor-level integer, floating-point, and vector instruction sets.

Use cases

• verify a RISC-V processor implementation against the ISA spec
• run compliance tests for RV32 and RV64 cores
• test floating-point and vector extensions of a RISC-V CPU
• validate supervisor-level instructions in a RISC-V simulator
• regression-test a custom RISC-V core during development

When to choose

• you are implementing or verifying a RISC-V processor, simulator, or emulator
• you need the canonical ISA-level unit tests maintained by the RISC-V community

When to avoid

• you need application-level or software testing tools rather than CPU instruction tests
• you are not working with RISC-V hardware or simulation
• you need a turnkey compliance certification suite with formal reporting

Facets

library · maturity active

testing developer-tools hardware embedded-systems developer-tools cli cpp risc-v processor-verification assembly unit-tests cpu-architecture linux

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