riscv-boom/riscv-boom

Health v2 · maintenance only

Adoption not part of the score

2226 stars · 524 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

BOOM (Berkeley Out-of-Order Machine) is a synthesizable, parameterizable open-source RV64GC RISC-V processor core written in the Chisel hardware construction language. It is a high-performance out-of-order core intended primarily for computer architecture research, instantiated via the Chipyard SoC generator rather than run standalone.

Use cases

• design and simulate a high-performance out-of-order RISC-V CPU core
• run computer architecture research with a parameterizable open-source processor
• synthesize a RISC-V core for FPGA or ASIC implementation
• boot Linux and run SPEC benchmarks on an open-source core
• generate custom SoCs with an out-of-order core using Chipyard
• study modern superscalar microarchitecture source code

When to choose

• you need a synthesizable, parameterizable out-of-order RISC-V core for research or silicon
• you want an FPGA-deployable high-performance core via Chipyard/FireSim
• you are studying or extending a modern OoO microarchitecture in Chisel

When to avoid

• you need a simple, small in-order embedded core (use Rocket or other simple cores)
• you want a standalone repository that builds a runnable CPU without Chipyard
• you need a commercial, verified production processor with support guarantees

Facets

library · maturity active

simulation compiler hardware cross-platform risc-v chisel cpu-core out-of-order rtl rocket-chip fpga asic processor-design scala processors computer-architecture research linux macos

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