# riscv-boom/riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

Repository: https://github.com/riscv-boom/riscv-boom
Canonical: https://ross.abutalabs.com/products/riscv-boom
Language: Scala
License: BSD-3-Clause
License Family: permissive
Topics: riscv, boom, chisel, rtl, rocket-chip, scala, riscv-boom, berkeley
Last push: 2026-08-26T07:47:19+00:00

## Health v2 (maintenance only)
Score: 67/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 99, release rhythm 8, longevity 100
- inputs: {"age_days": 4607, "days_push": 7, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2226, forks 524 (observed 2026-08-28T04:06:28.807252+00:00)

## What it is
BOOM (Berkeley Out-of-Order Machine) is a synthesizable, parameterizable open-source RV64GC RISC-V processor core written in the Chisel hardware construction language. It is a high-performance out-of-order core intended primarily for computer architecture research, instantiated via the Chipyard SoC generator rather than run standalone.

## Use cases
- design and simulate a high-performance out-of-order RISC-V CPU core
- run computer architecture research with a parameterizable open-source processor
- synthesize a RISC-V core for FPGA or ASIC implementation
- boot Linux and run SPEC benchmarks on an open-source core
- generate custom SoCs with an out-of-order core using Chipyard
- study modern superscalar microarchitecture source code

## When to choose
- you need a synthesizable, parameterizable out-of-order RISC-V core for research or silicon
- you want an FPGA-deployable high-performance core via Chipyard/FireSim
- you are studying or extending a modern OoO microarchitecture in Chisel

## When to avoid
- you need a simple, small in-order embedded core (use Rocket or other simple cores)
- you want a standalone repository that builds a runnable CPU without Chipyard
- you need a commercial, verified production processor with support guarantees

## Facets
- artifact type: library
- maturity: active
- function: simulation, compiler
- domain: hardware
- platform: cross-platform
- tags: risc-v, chisel, cpu-core, out-of-order, rtl, rocket-chip, fpga, asic, processor-design, scala, processors, computer-architecture, research, linux, macos

## Member repositories
- riscv-boom/riscv-boom (main) score 67

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:28.807252+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:44:54.103867+00:00, confidence not recorded.
  - readme: https://github.com/riscv-boom/riscv-boom (fetched 2026-08-28T04:06:28.807252+00:00, sha 7b69f279ee3d)
- Data as of 2026-08-30T08:39:29.467469+00:00.