XUANTIE-RV/openc910

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

1470 stars · 398 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

OpenC910 is the open-source RTL (Verilog) implementation of T-Head's Xuantie C910 RISC-V processor core, released under Apache-2.0. It includes an RTL simulation environment (smart_run) with testbenches, test cases, and Makefile-driven workflows supporting Verilator, iverilog, VCS, and irun.

Use cases

• simulate a RISC-V CPU core in Verilator
• study open-source high-performance RISC-V core RTL
• integrate a RISC-V processor core into a custom SoC
• run test cases against C910 RTL in a testbench
• customize and fork an open RISC-V out-of-order core

When to choose

• you need the actual C910 RTL source for SoC integration or research
• you want to simulate or verify a production-grade RISC-V core
• you are studying industrial RISC-V microarchitecture in Verilog

When to avoid

• you need a software toolchain or SDK rather than hardware RTL
• you want a simple, small FPGA-friendly soft core
• you need active community development rather than a maintained reference release

Facets

library · maturity maintenance

simulation embedded hardware embedded-systems cli risc-v cpu-core verilog rtl open-source-hardware processor-design linux

Member repositories

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