OSCPU/NutShell

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

1545 stars · 261 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

NutShell is an open-source RISC-V processor (SoC) designed by students at UCAS as part of the OSCPU project, written in Chisel/Scala. It supports riscv64/32, can run Linux (including Debian on FPGA), and generates Verilog via mill for simulation or FPGA deployment.

Use cases

• learning how to design a RISC-V CPU core
• running Linux on a custom RISC-V SoC on an FPGA
• simulating a RISC-V processor with a ready-to-run image
• generating Verilog from Chisel for chip design study
• building a Vivado FPGA project for boards like PYNQ or ZedBoard
• teaching computer architecture with an open-source chip project

When to choose

• you want an educational, student-built RISC-V core to study or modify
• you need a RISC-V SoC that boots Linux on FPGA boards like PYNQ or ZedBoard
• you want to experiment with Chisel-based processor design and simulation

When to avoid

• you need a production-grade, commercially supported RISC-V processor
• you require a license-permissive codebase (license is non-standard)
• you want a high-performance out-of-order core like BOOM or a mature vendor IP

Facets

library · maturity active

simulation compiler hardware embedded-systems operating-systems risc-v soc chisel scala processor-design fpga education verilog-generation linux

Member repositories

For agents

markdown · JSON · MCP: product_card(name="OSCPU/NutShell")