# OSCPU/NutShell

RISC-V SoC designed by students in UCAS

Repository: https://github.com/OSCPU/NutShell
Canonical: https://ross.abutalabs.com/products/nutshell
Homepage: https://oscpu.github.io/NutShell-doc/
Language: Scala
License: NOASSERTION
License Family: other
Last push: 2026-08-18T05:03:42+00:00

## Health v2 (maintenance only)
Score: 67/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 98, release rhythm 8, longevity 100
- inputs: {"age_days": 2248, "days_push": 15, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1545, forks 261 (observed 2026-08-28T04:05:01.495679+00:00)

## What it is
NutShell is an open-source RISC-V processor (SoC) designed by students at UCAS as part of the OSCPU project, written in Chisel/Scala. It supports riscv64/32, can run Linux (including Debian on FPGA), and generates Verilog via mill for simulation or FPGA deployment.

## Use cases
- learning how to design a RISC-V CPU core
- running Linux on a custom RISC-V SoC on an FPGA
- simulating a RISC-V processor with a ready-to-run image
- generating Verilog from Chisel for chip design study
- building a Vivado FPGA project for boards like PYNQ or ZedBoard
- teaching computer architecture with an open-source chip project

## When to choose
- you want an educational, student-built RISC-V core to study or modify
- you need a RISC-V SoC that boots Linux on FPGA boards like PYNQ or ZedBoard
- you want to experiment with Chisel-based processor design and simulation

## When to avoid
- you need a production-grade, commercially supported RISC-V processor
- you require a license-permissive codebase (license is non-standard)
- you want a high-performance out-of-order core like BOOM or a mature vendor IP

## Facets
- artifact type: library
- maturity: active
- function: simulation, compiler
- domain: hardware, embedded-systems, operating-systems
- platform: -
- tags: risc-v, soc, chisel, scala, processor-design, fpga, education, verilog-generation, linux

## Member repositories
- OSCPU/NutShell (main) score 67

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:01.495679+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T04:30:35.107326+00:00, confidence not recorded.
  - readme: https://github.com/OSCPU/NutShell (fetched 2026-08-28T04:05:01.495679+00:00, sha 6004dffa1c4a)
  - homepage: https://oscpu.github.io/NutShell-doc/ (fetched 2026-08-29T11:31:40.130800+00:00, sha cc67e8022a98)
- Data as of 2026-08-30T08:39:29.467469+00:00.