YosysHQ/nextpnr

Health v2 · maintenance only

Adoption not part of the score

1735 stars · 339 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

nextpnr is a vendor-neutral, timing-driven, open-source FPGA place and route tool written in C++. It supports multiple FPGA architectures including Lattice iCE40/ECP5/Nexus, Gowin, Cologne Chip GateMate, and experimental backends for Cyclone V, MachXO2, and Xilinx 7-series devices.

Use cases

• implement an FPGA design from Yosys-synthesized netlist to bitstream
• run place and route for Lattice iCE40 or ECP5 FPGAs without vendor tools
• experiment with custom FPGA architectures via the generic backend
• do timing-driven P&R for Gowin or GateMate devices
• build a fully open-source FPGA toolchain with Yosys and nextpnr

When to choose

• you want a FOSS FPGA flow avoiding vendor proprietary tools
• your target device is one of the supported architectures
• you need timing-driven placement and routing with a Python-scriptable API

When to avoid

• your FPGA is from a vendor not yet supported (e.g. most Xilinx or Intel devices)
• you need vendor-verified bitstreams for production with strict timing guarantees
• you only need synthesis without place and route

Facets

cli-tool · maturity active

compiler simulation developer-tools hardware embedded-systems developer-tools windows cli cross-platform fpga place-and-route eda open-source-hardware yosys ice40 ecp5 timing-driven linux macos

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markdown · JSON · MCP: product_card(name="YosysHQ/nextpnr")