NEORV32 RISC-V Processor
Some data may be outdated — see provenance labels.
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. observed · 2026-09-29
Health v2 · maintenance only
97/100
- Activity 97
- Release rhythm 96
- Longevity 100
How is this computed?
round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10) — computed 2026-10-21. Adoption (stars, forks) is never an input.
- gap_med: 19.0
- age_days: 2310
- days_rel: 30
- days_push: 23
- n_releases_24m: 31
Adoption not part of the score
2283 stars · 390 forks observed · 2026-09-29
Summary
No AI-extracted summary yet.
Member repositories
| Repository | Role | Health v2 |
|---|---|---|
| stnolting/neorv32 | main | 97 |
| stnolting/neoTRNG | plugin | 69 |
| stnolting/fpga_puf | plugin | 10 |
| stnolting/riscv-gcc-prebuilt | infra | 10 |
| stnolting/captouch | plugin | 10 |
| stnolting/neorv32-verilog | plugin | 10 |
| stnolting/neorv32-setups | examples | 76 |
For agents
markdown · JSON · MCP: product_card(name="stnolting/neorv32")
Data as of 2026-10-19T08:05:51.212177+00:00 · Report a problem