stnolting/neorv32

Health v2 · maintenance only

Adoption not part of the score

2242 stars · 377 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

NEORV32 is a customizable 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. It bundles the CPU, SoC peripherals, a software framework, and test infrastructure into a self-contained package targeting FPGA and ASIC designs.

Use cases

• implement a RISC-V soft-core CPU on an FPGA
• build a custom microcontroller SoC in VHDL
• learn digital design and RISC-V architecture
• integrate an auxiliary controller into a larger SoC design
• synthesize a RISC-V processor for ASIC
• prototype embedded software on a customizable RISC-V core

When to choose

• you need a small, customizable, RISC-V-compliant soft-core written in VHDL
• you want an out-of-the-box SoC with CPU, peripherals, and software framework included
• you target both FPGA and ASIC flows with platform-independent RTL
• you are a beginner looking for a well-documented open-source processor project

When to avoid

• you need a high-performance application-class processor rather than an MCU-class core
• your project requires SystemVerilog-native sources rather than VHDL or auto-converted Verilog
• you need hard real-time multi-core or out-of-order execution features

Facets

library · maturity active

embedded simulation sdk testing embedded-systems hardware programming-languages embedded cross-platform risc-v soft-core-cpu vhdl soc microcontroller fpga asic verilog open-source-hardware

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