# stnolting/neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Repository: https://github.com/stnolting/neorv32
Canonical: https://ross.abutalabs.com/products/neorv32
Homepage: https://stnolting.github.io/neorv32/
Language: VHDL
License: BSD-3-Clause
License Family: permissive
Topics: risc-v, soft-core, vhdl, fpga, soc, microcontroller, processor, cpu, verilog, asic
Last push: 2026-08-22T05:33:20+00:00

## Health v2 (maintenance only)
Score: 99/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 99, release rhythm 99, longevity 100
- inputs: {"age_days": 2262, "days_push": 11, "days_rel": 11, "gap_med": 17.5, "n_releases_24m": 33}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2242, forks 377 (observed 2026-08-28T04:06:29.803557+00:00)

## What it is
NEORV32 is a customizable 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. It bundles the CPU, SoC peripherals, a software framework, and test infrastructure into a self-contained package targeting FPGA and ASIC designs.

## Use cases
- implement a RISC-V soft-core CPU on an FPGA
- build a custom microcontroller SoC in VHDL
- learn digital design and RISC-V architecture
- integrate an auxiliary controller into a larger SoC design
- synthesize a RISC-V processor for ASIC
- prototype embedded software on a customizable RISC-V core

## When to choose
- you need a small, customizable, RISC-V-compliant soft-core written in VHDL
- you want an out-of-the-box SoC with CPU, peripherals, and software framework included
- you target both FPGA and ASIC flows with platform-independent RTL
- you are a beginner looking for a well-documented open-source processor project

## When to avoid
- you need a high-performance application-class processor rather than an MCU-class core
- your project requires SystemVerilog-native sources rather than VHDL or auto-converted Verilog
- you need hard real-time multi-core or out-of-order execution features

## Facets
- artifact type: library
- maturity: active
- function: embedded, simulation, sdk, testing
- domain: embedded-systems, hardware, programming-languages
- platform: embedded, cross-platform
- tags: risc-v, soft-core-cpu, vhdl, soc, microcontroller, fpga, asic, verilog, open-source-hardware

## Member repositories
- stnolting/neorv32 (main) score 99

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:29.803557+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:44:04.939463+00:00, confidence not recorded.
  - readme: https://github.com/stnolting/neorv32 (fetched 2026-08-28T04:06:29.803557+00:00, sha 533a24811bf4)
  - homepage: https://stnolting.github.io/neorv32/ (fetched 2026-08-29T10:24:19.924147+00:00, sha 2435d21597f8)
- Data as of 2026-08-30T08:39:29.467469+00:00.